1. Field of the Invention
The present invention is directed toward the field of building custom memory systems cost-effectively for a wide range of markets.
2. Art Background
The memory capacity requirements of computers in general, and servers in particular, are increasing at a very rapid pace due to several key trends in the computing industry. The first trend is 64-bit computing, which enables processors to address more than 4 GB of physical memory. The second trend is multi-core CPUs, where each core runs an independent software thread. The third trend is server virtualization or consolidation, which allows multiple operating systems and software applications to run simultaneously on a common hardware platform. The fourth trend is web services, hosted applications, and on-demand software, where complex software applications are centrally run on servers instead of individual copies running on desktop and mobile computers. The intersection of all these trends has created a step function in the memory capacity requirements of servers.
However, the trends in the DRAM industry are not aligned with this step function. As the DRAM interface speeds increase, the number of loads (or ranks) on the traditional multi-drop memory bus decreases in order to facilitate high speed operation of the bus. In addition, the DRAM industry has historically had an exponential relationship between price and DRAM density, such that the highest density ICs or integrated circuits have a higher $/Mb ratio than the mainstream density integrated circuits. These two factors usually place an upper limit on the amount of memory (i.e. the memory capacity) that can be economically put into a server.
One solution to this memory capacity gap is to use a fully buffered DIMM (FB-DIMM), and this is currently being standardized by JEDEC. FIG. 1A illustrates a fully buffered DIMM. As shown in FIG. 1A, memory controller 100 communicates with FB-DIMMs (130 and 140) via advanced memory buffers (AMB) 110 and 120 to operate a plurality of DRAMs. As shown in FIG. 1B, the FB-DIMM approach uses a point-to-point, serial protocol link between the memory controller 100 and FB-DIMMs 150, 151, and 152. In order to read the DRAM devices on, say, the third FB-DIMM 152, the command has to travel through the AMBs on the first FB-DIMM 150 and second FB-DIMM 151 over the serial link segments 141, 142, and 143, and the data from the DRAM devices on the third FB-DIMM 152 must travel back to the memory controller 100 through the AMBs on the first and second FB-DIMMs over serial link segments 144, 145, and 146.
The FB-DIMM approach creates a direct correlation between maximum memory capacity and the printed circuit board (PCB) area. In other words, a larger PCB area is required to provide larger memory capacity. Since most of the growth in the server industry is in the smaller form factor servers like 1 U/2 U rack servers and blade servers, the FB-DIMM solution does not solve the memory capacity gap for small form factor servers. So, clearly there exists a need for dense memory technology that fits into the mechanical and thermal envelopes of current memory systems.